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1 features ? dtv-soc for digital terrestrial television (dtt) ? on-chip dvb-t cofdm demodulator with fec. ? 6 video dacs on-chip, for composite or component (rgb or y u/v) analog video ? twin pal/ntsc dencs ? low power (<1.4w typical) ? low component count ? unified sdram controller ?i 2 s digital audio input ?i 2 s and s/pdif digital audio outputs ? mpeg-2 audio & video decoders ? powerpc 405 tm cpu core with 16k/16k cache, memory manager and virtual memory system ? complete linux-based software development kit (sdk) ?ide interface ? inputs for external mpeg-2 transport streams, allowing support for external demodulators (e.g. cable tv, satellite tv) ? conditional access (ca) dvb-descrambler ? smart card interface ? infrared & uart interface ? dvb-compatible common interface (ci) control and bitstream interfaces ? multi-stream multiplexing to support internal and external demodulators ? external modem support interface ? supports macrovision tm copy protection - ( zl10311 only; available to macrovision license holders only) ?dolby ? digital* decoding - (zl10311 only; available to dolby ? digital* license holders only - *awaiting certification) issue 1.0 november 2002 ordering information zl10310/gac 388 ball epbga zl10311/gac 388 ball epbga 0 0 c to +70 0 c zl10310/zl10311 digital television dvb-t-on-a-chip processor data sheet figure 1 - block diagram of zl10310 and zl10311 aux bus sdram 1 bus bitstream o/p /second smart card bitstream i/p bitstream multiplexing & control peripherals flash ide ci control system demultiplex de- scrambler audio decoder cached powerpc 405 sub system cofdm demodulator & fec agc b sdram controller video scaler / blender stereo audio dac i s 2 comp video y+u/v rgb analog video de-mod /jtag adc in /de-mod jtag r smart card codec/modem i c uart/irda bit i/o 2 sdram controller sdram 0 bus (optional) video decoder 8k boot rom power management adcin extin s/pdif zl10310 / zl10311 dtv-soc video dencs /dacs
zl10310/zl10311 data sheet 2 zarlink semiconductor inc. applications ? low power, small footprint tv adaptors ? integrated digital televisions (idtv) ? digital terrestrial set-top boxes ? dtt / dvd combo ? dvb-t radio receivers ? terrestrial / satellite combo ? terrestrial / cable combo ? terrestrial / ip (internet protocol) combo description zarlink semiconductor has responded to market demand by integrating its key dvb-t compliant cofdm demodulation technology with set top box functionality (mpeg-2 a/v decoder and system interfaces) together with a high performance cpu to offer a ?dvb-t on-a-chip? solution. the zl10310 dvb-t on-a-chip, can address a wide range of dvb-t consumer electronic products. at the entry level it can be used to build ultra-compact free-to-view digital tv adaptors (such as for freeview in the uk), yet consumes less than 4w of power in full operational mode. this level of compactness also considerably eases the integration of dvb-t receiver technology inside integrated digital tv sets (idtv?s) where space considerations and thermal management are key design issues. the zl10310 is based upon an industry standard powerpc 405 tm risc processor, which has virtual and memory management sub-systems. this permits the device to be effectively deployed in compelling applications such as interactive digital tv which are able to exploit the superior processing performance offered by the powerpc ? processor core. the powerpc ? provides an ideal platform for running robust open standard operating systems such as linux which can benefit system developers in a number of key areas: ? unified software development environment, from entry level basic channel zapper systems through to fully interactive high performance digital set top boxes. ? re-use of software code from multiple projects ? exploit software code developed in the linux community. ? low cost-per-seat software development environment. ? familiar software development environment. ? royalty free. also available is the zl10311 dvb-t on-a-chip, which additionally offers dolby ? digital 1 multi-channel audio decoding, and macrovision tm copy protection for applications requiring dolby ? audio and pay tv services. 1. the zl10311 device is awaiting dolby certification
data sheet zl10310/zl10311 3 zarlink semiconductor inc. table of contents 1.0 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.0 device interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.0 typical digital television (dtv) receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.0 functional blocks overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 boot rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 clock generation block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 coded orthogonal frequency division multiplex (cofdm) demodulator . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.4 mpeg audio decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.5 mpeg-2 video decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.6 powerpc 405tm processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.7 transport engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.8 video display system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.0 physical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.0 zl10310/zl10311 388-pin package pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.1 pin types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2 front end interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.3 video dac outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4 sdram interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.5 bit stream interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.6 auxiliary external bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.7 peripheral port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.8 modem/codec interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.9 smart card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.10 general purpose input output interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.11 simplified general purpose input output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.12 inter integrated circuit (i2c) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.13 inter ic sound (i2s) audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.14 clock and reset interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.15 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.16 reserved connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.0 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 ac and dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 ibm ? , the ibm logo, powerpc ? and powerpc405 tm are trademarks of international business machines corporation. dolby ? is a trademark of dolby laboratories. supply of this implementation of dolby technology does not convey a license or imply a right under any patent, or any other industrial or intellectual property right of dolby laboratories, to use this implementation in any finished end-user or ready-to-use final product. it is hereby notified that a license for such use is required from dolby laboratories 1 . this device is protected by us patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. use of the macrovision anticopy process in the device is licensed by macrovision for non-commercial, home and limited exhibition use only. reverse engineering or disassembly is prohibited. a valid macrovision license must be in effect between the purchaser of the zl10311 ic and macrovision corporation. additional per-chip royalties may be required and are payable by the purchaser to macrovision. 1. the zl10311 device is awaiting dolby certification
zl10310/zl10311 data sheet 4 zarlink semiconductor inc. 1.0 device overview zarlink semiconductor has designed the zl10310 and zl10311 system on a chip (soc) devices specifically for dvb-t applications. integrating a high performance powerpc 405 tm processor with robust industry proven mpeg-2 audio and video decoding, osd and a cofdm demodulator, the zl10310 and zl10311 deliver the performance and functionality required for advanced digital tv entertainment products. it enables the rapid design and manufacture of cost-effective idtv and digital audio visual home entertainment centers. the enhanced zl10311 also supports dvd playback with up to six dolby ? digital 1 audio channels. in addition, by integrating the cofdm demodulator, the zl10310 and zl10311 enable the implementation of very small footprint tv adaptor modules. 2.0 device interfaces the following peripheral interfaces are available to the user. apart from possible level translation and connector buffering, no external devices are required to support any of the interfaces. ? 10-bit input that may be configured for an adc input to the internal cofdm demodulator ? additional input bus for additional mpeg-2 transport sources ? agc (pwm) outputs for a terrestrial tuner ? serial control port for a digital tuners ? common interface control and bitstream interfaces for an external descrambler ? normal pc (pcmcia) memory module interface for local software updates ? unified 64 mbit sdram interface for all decoders and powerpc 405 tm ? additional sdram interface for high end systems requiring increased memory bandwidth ? static memory interface for flash and external peripherals ? ide/atapi interface for hard disk and dvd drives ? external dma channel and interrupts ? six analog video outputs give full flexibility on rgb, s-vhs, and composite signals (with and without osd) ?i 2 s input port from external digital stereo source ?three i 2 s ports to external audio dacs for main, surround, and centre channels ?dolby ? surround sound control signals ? sony/philips digital interface (s/pdif) if not required in a particular system, any of the peripheral interfaces can be replaced by individual i/o bits from internal general purpose registers. these can then be used for additional purpose, such as interfacing to switches and displays. ? full rs232 interface to an external modem or a 4 wire interface to a codec ? irda interface or an additional asynchronous serial interface ? synchronous serial interface for eeprom, etc. ? two smart card interfaces (one instead of a common interface) ? general purpose i 2 c interface ? general purpose timer for infrared (ir) decoding ? general purpose individual bit i/os 1. the zl10311 device is awaiting dolby certification
data sheet zl10310/zl10311 5 zarlink semiconductor inc. figure 2 - block diagram of a typical zl10310-based free to air tv adaptor 3.0 typical digital television (dtv) receiver figure 2 shows a typical free to air tv receiver block diagram employing a zl10310 dtv-soc device. in its minimal configuration, the zl10310 dtv-soc device only requires a single 64 mbit sdram, an audio dac, and a flash rom, which are in addition to a dvb-t tuner front end and a 10-bit analog to digital converter. the terrestrial tuner section performs an independent down conversion of the received dvb-t signal from the antenna, to an if frequency in the range of 30mhz to 57mhz, dependent on television system (typically 36.17mhz center frequency, with 4mhz span). the analogue if is then converted to the digital domain, with a 10-bit adc, clocked at 20.48mhz and the resulting digital output is centered on 15.69mhz. this digital signal is applied to the zl10310 via the adc_in[9:0] input pins, in the form of a 10-bit parallel signal. the zl10310 converts the digitized if from a terrestrial tv tuner into an mpeg-2 transport stream, which can be optionally de-scrambled (if ca scrambling is used by the broadcaster), and de-multiplexed into separate packetised elementary streams (pes), which are routed to the mpeg audio and video decoders, and si data to the powerpc 405 tm subsystem. decoded video can then be mixed and optionally scaled with on-screen display (osd) graphics generated by the dtv application software. the resultant combination of video and graphics are then routed to the pal/ntsc digital encoders (dencs) for display on the tv via the on-chip 10-bit video dacs. decoded audio is output directly from the audio decoder sub-system to the i 2 s and s/pdif (sony/philips digital interface) outputs. zl10310 dtv-soc comp video analog video rgb or y u/v digital audio (i s) d a c analog audio 2 aux bus aux bus 8mb flash external peripherals sdram sdram1 bus error 27mhz vcxo clk 27in 20.48mhz crystal oscillator cofdm clock terrestrial tuner adcin agc b adcclk a d c 20.48mhz bitstream o/ps bitstream i/ps common interface tuner control serial eeprom infrared sensor
zl10310/zl10311 data sheet 6 zarlink semiconductor inc. 4.0 functional blocks overview 4.1 boot rom program execution on the power pc ? normally starts from address 0xfffffffc after the internal reset has gone inactive. this would normally be an address in the external flash rom (enabled by bi_cs0), but, by forcing the sgpio2_3 pin low during reset, it is possible to boot from the internal 8k boot rom. the zl10310 and zl10311 devices contain an 8k boot rom containing code, which is executed under the noted conditions above following a complete system reset (i.e. when main power has been removed from the zl10310 or zl10311). the code installed on the boot rom, allows the zl10310/zl10311 to undertake any of the following 4 functions after a complete reset: 1. enter isp (in-system programmable) mode, in which the software in the internal boot rom will try booting from an spi or i 2 c eeprom. 2. try booting from an atmel serial flash device (at45xxxxx) first, if that fails then enter isp mode. 3. try booting from an asynchronous parallel flash device connected to the ebiu bus (cs0) first. if that fails, then try booting from spi or i 2 c eeprom or serial flash. 4. enter debug/monitor mode in which a command prompt is available for debugging registers, downloading code, etc. 4.2 clock generation block the zl10310/zl10311 devices use two separate external clock sources to provide all the clocks required; a 27mhz external voltage controlled crystal oscillator (vcxo), and a 20.48mhz external crystal oscillator. a standard 27mhz input to the systems pll is supplied from an external vcxo. outputs from this pll are used to clock the various internal mpeg decoders, the powerpc ? micro controller system, and the external sdram. the frequency can be adjusted in the ppm range, using a voltage produced by the pulse width modulated frequency error signal, available from gpio port gp29. the 27mhz input also drives a separate audio pll that is dedicated to providing 256/512 times the audio sampling rate for the audio decoder and external audio dac. the cofdm de-modulators have their own pll driven from an internal 20.48mhz oscillator. an external crystal is required for this oscillator.
data sheet zl10310/zl10311 7 zarlink semiconductor inc. 4.3 coded orthogonal frequency division multiplex (cofdm) demodulator the cofdm demodulator is used to demodulate a digitized cofdm modulated if signal from the tv tuner, and ultimately convert the resulting mpeg-2 transport stream to the mpeg-2 demultiplexer. the digitized if is converted to a complex baseband signal centered on zero frequency. it also removes adjacent channel interference prior to a time-to-frequency fast fourier transform (fft). the resulting signals are then sent to a digital re-timing block, symbol sync, carrier recovery, and timing recovery. an agc signal, with a variable mark space ratio, is provided to control the signal levels in the tuner sections of the receiver. forward error correction (fec) is performed by viterbi decoding of the convolutional coded data, followed by de-interleaving, reed-solomon decoding, and energy dispersal de-randomising. the output is mpeg-2 transport stream packets, in byte format. the cofdm demodulator is fully compliant with the etsi 300 744 and digital television group (dtg) specifications. key features are: ? fft processor operates in 2k and 8k carrier mode. 1 ? all hierarchical and non-hierarchical constellations. ? automatic digital carrier recovery over a wide range of offsets without the need for afc ? automatic digital carrier recovery without the need for a vcxo ? common phase error correction ? channel correction using time and frequency filtering ? automatic co - channel protection, frame sync, and fast channel re- acquisition ? internal controller handles all tracking and acquisition ? viterbi decoding with code rates of 1/2, 2/3, 3/4, 5/6, 6/7, and 7/8 ? automatic synchronization and code rate detection ? constraint length k = 7 ? trace back depth of 128 ? de-interleaver followed by dvb reed solomon error correction ? de-randomizer and common interface formatting 4.4 mpeg audio decoder the mpeg audio decoder produces dual channel outputs from mpeg -1 or mpeg -2 transport streams with a maximum rate of 640 kbit/sec. it supports sampling rates of 32, 44.1, and 48 khz, plus the half rate options. all sampling rates, plus 512/256 fs, are produced from an internal pll. a version of the device is available which produces six channels of audio output for holders of the dolby ? digital 2 license. ? decodes mpeg-1 and dual channel mpeg-2 audio ? performs mpeg-1 audio parsing and mpeg-2 packetised elementary stream (pes) audio parsing, or accepts audio elementary streams ? supports 32khz, 44.1 khz, and 48 khz sampling rates plus the half rate options ? all sampling rates, plus 512/256 fs, derived from an internal pll ? 64 step audio attenuation with smooth step transitions ? spdif output meeting iec1937 specifications ? re-locatable ancillary data region ? audio clip mode ? dolby ? ac3 option 2 1. for details on 8k carrier performance and use, please consult zarlink field applications 2. the zl10311 device is awaiting dolby certification
zl10310/zl10311 data sheet 8 zarlink semiconductor inc. 4.5 mpeg-2 video decoder the mpeg-2 video decoder provides complete decoding and synchronized playback of mpeg-2 mp@ml (main profile at main level) video streams. it supports the decoding of still pictures as well as moving video, with error concealment when necessary. a command driven local controller minimizes the amount of application software needed to control the decoding / channel change process. the decoder accepts pes from the transport de-multiplexer, with average rates of up to 15 mbps. pes header parsing supports the extraction of presentation time stamp (pts) values, which are then used by the audio/ video synchronization hardware. pes or es streams can be directly decoded from sdram in the video clip mode of operation. feature summary: ? packetised mpeg-2 mp @ ml video streams from the transport demultiplexer or from sdram ? mpeg-1 video (es) streams from sdram ? sustained bit rates from 1.5 mbps to 15 mbps. ? local processor driven by commands from the application processor ? sophisticated error concealment based on the use of stored motion vectors from the previous row ? supports the decoding of still images ? automatic or manual image re-sizing ? conversion of mpeg-1, 24 hz progressive scan, pictures to 60 hz interlaced (3:2 pull-down) 4.6 powerpc 405 tm processor an integrated powerpc 405 tm processor core is provided for applications and control software, and this provides approx. 150 drhystone mips with a clock of 108 mhz. it has instruction and data caches with lock down facilities such that defined areas can be used as general purpose ram. the processor has its own internal bus to which is attached the caches, all the peripherals, and a dma controller. code can thus be executed, using internal resources, whilst the mpeg decoders are using the sdram. this processor bus is also connected to an auxiliary external bus, which is used for flash code transfer during the power on routine, and for flash write operations. pcmcia, and ide data transfers also use this bus to provide data and address signals, but their respective control signals have dedicated pins. a bridge to the internal multi-master bus provides software access to the external sdram. all internal and external memory is in a unified address space, and a dma controller supports high speed data transfers. controllers are provided for two smart cards, an rs232 modem, a serial codec, an i 2 c master, a synchronous serial port, and an irda interface. individual bit i/o is also supported. key features: ? powerpc 405 tm processor core running at 108 mhz ? integrated instruction and data caches (16k/16k) with lock down ? integrated set top box peripheral controllers ? four channel dma controller for peripheral and data transfers ? dedicated internal processor bus with its own sdram controller and auxiliary bus ? bridge to the decoder multi-master bus and shared sdram ?real time counters ? watch dog timer ? interrupt controller
data sheet zl10310/zl10311 9 zarlink semiconductor inc. 4.7 transport engine the zl10310/zl10311 devices contain a dedicated hardware implementation of an mpeg/dvb transport stream de-multiplexer, with the configuration of this hardware controlled by application software. included in the hardware are synchronization, packet identifier (pid) filtering, clock recovery, de-scrambling, and table section filtering. pid filtered packets are stored in a local buffer, which can hold up to 10 packets before they are moved to the decoders or to memory queues in sdram. the queues are used for the tables containing system information. packets for three destinations can be moved concurrently out of the buffer. the hardware acts in conjunction with a transport assist processor, and the resultant hardware/software combination gives increased adaptability and extended processing capability. further parsing and filtering is possible, and interrupts can be generated to notify the processor when a given condition has been met. the transport assist processor can then read and manipulate packets whilst they are still in the transport packet buffer. it can then allow data to pass through to sdram or the decoders, or can record status information and optionally interrupt the application. key features: ? 32 pid values can be used to filter the transport stream ? flexible, hardware based, section filtering ? 64, 4 byte, filter blocks. ? filter blocks can be cascaded to provide deep filtering when necessary ? hardware cyclical redundancy check (crc) checking ? captured data is transferred to one of thirty two queues in sdram ? options to transfer complete transport packets with or without headers, or sections ? adaptation fields can be delivered to a separate queue ? hardware to extract pcr values with option for software filtering to remove long term jitter ? comprehensive error detection hardware ? integrated dvb descrambler 4.8 video display system the video display system provides multi-layered video. this features the on-screen display (osd) for menuing and mheg-5, the decoded video presentation system, and a video blending capability to merge the osd and video. the on-screen display system is designed to meet or exceed the specifications of major european broadcasters. the final image on the screen is constructed from five separate planes using a fixed display hierarchy. the screen hierarchy consists of: 1. cursor plane (top) 2. region-based graphics plane (typically used for epg and system menus) 3. video plane 4. still image plane (typically used for mheg-5) 5. background plane all planes, apart from the background plane, can be separately enabled. the graphics and image planes are region based, and driven by means of bitmaps controlled by a link-list processor. they can operate independently, but have nearly identical operational controls. the size of a bitmap region can vary between 4 pixels wide by 2 pixels deep, and 1k pixels wide and 1k pixels deep. the color resolution of a pixel within a region can be defined by 2, 4, 8, or 16 bits. the 16-bit option is for direct colors; the other options use color look up tables. the video presentation system is used to scale and process a decoded video signal. decoded video is stored in field stores contained in external sdram memory. prior to display it can be automatically scaled from the original resolution and aspect ratio up to pal or ntsc full screen size. if the encoded image has a 16:9 aspect ratio, but the display has a 4:3 aspect ratio, then any horizontal scaling factor necessary to fill the screen must be adjusted by
zl10310/zl10311 data sheet 10 zarlink semiconductor inc. a further factor of 4/3. alternatively, a factor of 3/4 can be applied vertically (letter box mode). video is displayed at the standard pal or ntsc field rates. synchronization signals for video presentation can be provided by either the video decoder itself (master mode), or the decoder can slave to incoming signals. the video blending system is used to blend the outputs from separate digital encoded video (denc) blocks for the video and osd systems on-chip: 1. rgb ? red green blue 2. y u/v 3. cvbs ? chroma video blanking and sync 5.0 physical specification the device is contained in a 388-ball enhanced plastic ball-grid array (388 epbga) package: ? body size: 27mm x 27mm ? ball count: 388 (includes 36 thermal balls) ? ball pitch: 1.0mm ? ball matrix: 26 x 26 (partially populated with a 6 x 6 gnd matrix in the centre) ? ball diameter 0.60mm ? total package thickness 2.65mm package is viewed from the top side (i.e. through top of the package). note ball a1 is non-chamfered corner. figure 3 - package view and ball positions a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 2 3 4 5 6 7 8 9 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 2 3 4 5 6 7 8 9 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 pi n a1 ident pin a1 ident
data sheet zl10310/zl10311 11 zarlink semiconductor inc. 6.0 zl10310/zl10311 388-pin package pin descriptions this section explains the zl10310 and zl10311 device pin functions. the following tables are segmented by signal functions. many of the pins listed below have multiple functions, and in these cases there is information on how the multiplexed function connects to the pin. many references are made to register settings throughout the pin descriptions. the details of the zl10310 and zl10311 registers can be found in the hardware design manual for the zl103xx family of integrated digital television processors (publication dm5797), available to customers on request, subject to nda. 6.1 pin types 6.2 front end interfaces i an input type with no designator indicates that the signal must be produced by a device using 3.3v outputs, and esd protection is provided. there is no internal pull up, so unused inputs should be tied high or low. io pin type indicates that the pin can be programmed with control bits to be used as an input or an output. b pin type indicates that the pin function can alternate between an input and output depending on the use at that instant i.e. it is bi-directional. out characteristics are the same as an out pin. od is an open drain output. o is a standard 3.3 v, 65 ohm, output, unless otherwise specified. dc drive is 8.2ma/5.4ma @ vh/vl respectively. maximum slew rate is 75ma/ns, unless otherwise specified . 5v is a 5v tolerant input or output. an input type with a 5v designator indicates that the input tolerates 5v signals. there is no internal pull up. pin name pin no. function pin type description notes adcclk r02 adcclk o sampling clock output to external tuner if analog to digital converter. clock = 20.48mhz. agc[0] l02 tuner agc control o 5v master agc control output to external tv tuner 1 agc[1] m03 tuner agc control offset o 5v secondary agc control output to external tv tuner. used to provide a differential agc feed to external tv tuner, if required. 1 gpp[0] l01 tuner_scl o 5v external tv tuner control bus - clock output 1, 6 gpp[1] n04 tuner_sda b 5v external tv tuner control bus - data input/output. 1, 6 ext_in[0] k01 ed1_mdo[7] (msb) i external demodulator 1 digital input - data bit 7 (msb) 5, 7 dv2_in_data[7] (msb) i reserved 7 rw_tdo o debug interface - jtag tdo (data out) 3
zl10310/zl10311 data sheet 12 zarlink semiconductor inc. ext_in[1] k02 ed1_mdo[6] i 5v external demodulator 1 digital input - data bit 6 1, 5, 7 rw_tdi i 5v debug interface - jtag tdi (data in) 1, 3 da_ser_datai i 5v digital audio serial data input. main left and right serial audio data at a rate of 64fs. signal routed through to gp12 (not bonded out) 1, 4 ext_in[2] j01 ed1_mdo[5] i external demodulator 1 digital input - data bit 5 5, 7 dv2_in_data[6] i reserved 7 rw_halt i debug interface - jtag halt 3 ext_in[3] l03 ed1_mdo[4] i external demodulator 1 digital input - data bit 4 5, 7 dv2_in_data[5] i reserved 7 rw_tms i debug interface - jtag tms 3 ext_in[4] j02 ed1_mdo[3] i external demodulator 1 digital input - data bit 3 5, 7 dv2_in_data[4] i reserved 7 rw_tck i debug interface - jtag tck 3 ext_in[5] l04 ed1_mdo[2] i external demodulator 1 digital input - data bit 2 5, 7 dv2_in_data[3] i reserved 7 te s t [ 0 ] i te s t m o d e a - te s t p i n 0 ext_in[6] k03 ed1_mdo[1] i external demodulator 1 digital input - data bit 1 5, 7 dv2_in_data[2] i reserved 7 te s t [ 1 ] i te s t m o d e a - te s t p i n 1 ext_in[7] h02 ed1_mdo[0] (lsb) i external demodulator 1 digital input - data bit 0 (lsb) 5, 7 dv2_in_data[1] i reserved 7 te s t [ 2 ] i te s t m o d e a - te s t p i n 2 ext_in[8] g01 ed1_mval i external demodulator 1 digital input - data valid input 5 dv2_in_data[0] (lsb) i reserved 7 te s t [ 3 ] i te s t m o d e a - te s t p i n 3 ext_in[9] j03 ed1_mclk i external demodulator 1 digital input - clock input 5 dv2_pixel_clk i reserved te s t [ 4 ] i te s t m o d e a - te s t p i n 4 pin name pin no. function pin type description notes
data sheet zl10310/zl10311 13 zarlink semiconductor inc. adc_in[0] v03 cofdm_adcin[8] (msb) i cofdm digital input from ext. adc - data bit 8 (msb) 2, 5, 7 dv2_in_data[7] (msb) i reserved (when ext_in[0] used for jtag in debug) 7 ed2_mdo[7] (msb) i external demodulator 2 digital input - data bit 7 (msb) 7 adc_in[1] w03 cofdm_adcin[7] i cofdm digital input from ext. adc - data bit 7 2, 5, 7 ed2_mdo[6] i external demodulator 2 digital input - data bit 6 adc_in[2] aa02 cofdm_adcin[6] i cofdm digital input from ext. adc - data bit 6 2, 5, 7 dv2_in_data[6] i reserved (when ext_in[2] used for jtag in debug) 7 ed2_mdo[5] i external demodulator 2 digital input - data bit 5 7 adc_in[3] ab01 cofdm_adcin[5] i cofdm digital input from ext. adc - data bit 5 2, 5, 7 dv2_in_data[5] i reserved (when ext_in[3] used for jtag in debug) 7 ed2_mdo[4] i external demodulator 2 digital input - data bit 4 7 adc_in[4] y03 cofdm_adcin[4] i cofdm digital input from ext. adc - data bit 4 2, 5, 7 dv2_in_data[4] i reserved (when ext_in[4] used for jtag in debug) 7 ed2_mdo[3] i external demodulator 2 digital input - data bit 3 7 adc_in[5] ab02 cofdm_adcin[3] i cofdm digital input from ext. adc - data bit 3 2, 5, 7 dv2_in_data[3] i reserved (when ext_in[5] used for jtag in debug) 7 ed2_mdo[2] i external demodulator 2 digital input - data bit 2 7 adc_in[6] ac01 cofdm_adcin[2] i cofdm digital input from ext. adc - data bit 2 2, 5, 7 dv2_in_data[2] i reserved 7 ed2_mdo[1] i external demodulator 2 digital input - data bit 1 7 adc_in[7] aa04 cofdm_adcin[1] i cofdm digital input from ext. adc - data bit 1 2, 5, 7 dv2_in_data[1] i reserved 7 ed2_mdo[0] (lsb) i external demodulator 2 digital input - data bit 0 (lsb) 7 pin name pin no. function pin type description notes
zl10310/zl10311 data sheet 14 zarlink semiconductor inc. note 1: 5v tolerant connection to allow use of 5v tuner devices note 2: multiplex setup with cofdm register bit 0 = '1' note 3: multiplex setup with cicsel3 register bits 9:11 = '111' note 4: multiplex setup with cicsel3 register bit 6 = '1', and gpis2 register bits 24:25 = '01' note 5: multiplex setup with cofdm register bit 0 = '0' note 6: external pull-up to tuner vdd psu required on gppx lines. note 7: the adc_in [0:9] and ext_in [0:9] inputs on the front end interface are configured as ?big endian?. this means that bit [0] is the most significant bit (msb) for the multiplexed functions mapped to that pin. note 8: when the adc_in [0:9] and ext_in [0:9] pins are used to provide various alternative inputs within one application, then each set of inputs must have a tri-state buffer. the enables for these buffers should then be controlled by general purpose i/o pins . 6.3 video dac outputs note 1: video outputs capable of driving between 37.5ohm and 75ohm loads. adc_in[8] aa03 cofdm_adcin[0] (lsb) i cofdm digital input from ext. adc - data bit 0 (lsb) 2, 5, 7 dv2_in_data[0] (lsb) i reserved 7 ed2_moval i external demodulator 1 digital input - data valid input adc_in[9] ac02 dv2_in_pixel_clk i reserved ed2_moclk i external demodulator 1 digital input - clock input pin name pin no. pin type description notes dac_op0 ae15 o video triple-dac 1 output 1. 1, 2 dac_op1 ad15 o video triple-dac 1 output 2. 1, 2 dac_op2 ad13 o video triple-dac 1 output 3. 1, 2 dac_op3 ad10 o video triple-dac 2 output 1. 1, 2 dac_op4 af06 o video triple-dac 2 output 2. 1, 2 dac_op5 af10 o video triple-dac 2 output 3. 1, 2 dac1_cref_out af11 o de-coupling for triple dac 1 - to gnd dac1_gref_out af17 o de-coupling for triple dac 1 - to avdd dac1_rref_out ae13 o gain control for triple dac 1. 3 dac1_vref_in ae14 i voltage reference input (1.2v) for video triple-dac 1. 4 dac2_cref_out ae11 o de-coupling for triple dac 2 - to gnd dac2_gref_out af05 o de-coupling for triple dac 2 - to avdd dac2_rref_out ae09 o gain control for triple dac 2. 3 dac2_vref_in af07 i voltage reference input (1.2v) for video triple-dac 2 4 pin name pin no. function pin type description notes
data sheet zl10310/zl10311 15 zarlink semiconductor inc. note 2: triple dac output can be setup using the dencmux register to output any of the following types of video signal: rgb, cvbs, y u/v note 3: gain set using current adjust resistor to gnd. typically need 392ohms for a dac load of 37.5ohms. note 4: apply external reference (1.2v) when internal reference is not in use. 6.4 sdram interfaces the zl10310 and zl10311 devices have 2 independent sdram interfaces. the main sdram interface is sdram1 which is used as the main memory space for both the powerpc ? processor and video/audio decoding. if required a separate processor-only sdram interface can be used; this is the optional sdram0 interface. all the signals for the sdram1 and sdram0 interfaces are configured as ?big endian?, which signifies that bit [0] on both the address and data buses is the most significant bit (msb). pin name pin no. pin type description notes sd1_addr[00] d24 o sdram1 bus - address bit 0 (msb) sd1_addr[01] f26 o sdram1 bus - address bit 1 sd1_addr[02] f25 o sdram1 bus - address bit 2 sd1_addr[03] e25 o sdram1 bus - address bit 3 sd1_addr[04] e26 o sdram1 bus - address bit 4 sd1_addr[05] d26 o sdram1 bus - address bit 5 sd1_addr[06] l23 o sdram1 bus - address bit 6 sd1_addr[07] c26 o sdram1 bus - address bit 7 sd1_addr[08] a25 o sdram1 bus - address bit 8 sd1_addr[09] b23 o sdram1 bus - address bit 9 sd1_addr[10] b24 o sdram1 bus - address bit 10 sd1_addr[11] c23 o sdram1 bus - address bit 11 sd1_addr[12] c25 o sdram1 bus - address bit 12 sd1_addr[13] d25 o sdram1 bus - address bit 13 (lsb) sd1_data[00] n24 b sdram1 bus - data bit 0 (msb) sd1_data[01] n26 b sdram1 bus - data bit 1 sd1_data[02] m25 b sdram1 bus - data bit 2 sd1_data[03] t23 b sdram1 bus - data bit 3 sd1_data[04] l25 b sdram1 bus - data bit 4 sd1_data[05] k26 b sdram1 bus - data bit 5 sd1_data[06] k24 b sdram1 bus - data bit 6 sd1_data[07] j25 b sdram1 bus - data bit 7 sd1_data[08] j24 b sdram1 bus - data bit 8
zl10310/zl10311 data sheet 16 zarlink semiconductor inc. sd1_data[09] k25 b sdram1 bus - data bit 9 sd1_data[10] l26 b sdram1 bus - data bit 10 sd1_data[11] l24 b sdram1 bus - data bit 11 sd1_data[12] m26 b sdram1 bus - data bit 12 sd1_data[13] m24 b sdram1 bus - data bit 13 sd1_data[14] n25 b sdram1 bus - data bit 14 sd1_data[15] p25 b sdram1 bus - data bit 15 (lsb) sd1_dqmh h25 o sdram1 bus - data bus mask high. active high sd1_dqml j26 o sdram1 bus - data bus mask low. active high nsd1_ras g25 o sdram1 bus - row address strobe. active low. also known as sdram 1 command bit 2 (msb). nsd1_cas g24 o sdram1 bus - column address strobe. active low. also known as sdram 1 command bit 1. nsd1_we h24 o sdram1 bus - write enable. active low. also known as sdram 1 command bit 0 (lsb). sd1_clk g26 o sdram1 bus - clock output 1 nsd1_cs0 f24 o sdram1 bus - chip select 0. active low sd0_addr[00] ac26 o sdram0 bus. address bit 0 (msb) sd0_addr[01] ac24 o sdram0 bus. address bit 1 sd0_addr[02] ab25 o sdram0 bus. address bit 2 sd0_addr[03] ab26 o sdram0 bus. address bit 3 sd0_addr[04] ab24 o sdram0 bus. address bit 4 sd0_addr[05] aa24 o sdram0 bus. address bit 5 sd0_addr[06] aa25 o sdram0 bus. address bit 6 sd0_addr[07] y26 o sdram0 bus. address bit 7 sd0_addr[08] y25 o sdram0 bus. address bit 8 sd0_addr[09] v24 o sdram0 bus. address bit 9 sd0_addr[10] w24 o sdram0 bus. address bit 10 sd0_addr[11] y24 o sdram0 bus. address bit 11 sd0_addr[12] aa26 o sdram0 bus. address bit 12 sd0_addr[13] aa23 o sdram0 bus. address bit 13 (lsb) sd0_data[00] ae18 b sdram0 bus - data bit 0 (msb) pin name pin no. pin type description notes
data sheet zl10310/zl10311 17 zarlink semiconductor inc. note 1: sd0_clk / sd1_clk output is 50ohm impedance with 130ma/ns slew rate 6.5 bit stream interfaces the zl10310 and zl10311 devices have a fully dvb-compatible byte-wide common interface, which is a bitstream data input/output bus. there are multiplexed functions on these pins, and included is information on how to access these multiplexed signals. the multiplexed functions include access to address/data bits of the auxiliary external bus (configured on this interface to access pcmcia (pc) cards), risc trace debug ports, simplified gpio bus 1 and smart card interface 1. the data pins for output (mod[0:7]) and input (mid[0:7]) are configured as ?big endian?. this means that bit [0] is the most significant bit (msb) for the common interface and auxiliary bus signals. sd0_data[01] ad19 b sdram0 bus - data bit 1 sd0_data[02] ad20 b sdram0 bus - data bit 2 sd0_data[03] af20 b sdram0 bus - data bit 3 sd0_data[04] ad21 b sdram0 bus - data bit 4 sd0_data[05] ae21 b sdram0 bus - data bit 5 sd0_data[06] ae22 b sdram0 bus - data bit 6 sd0_data[07] af23 b sdram0 bus - data bit 7 sd0_data[08] ad23 b sdram0 bus - data bit 8 sd0_data[09] ad22 b sdram0 bus - data bit 9 sd0_data[10] af22 b sdram0 bus - data bit 10 sd0_data[11] af21 b sdram0 bus - data bit 11 sd0_data[12] ac21 b sdram0 bus - data bit 12 sd0_data[13] ae20 b sdram0 bus - data bit 13 sd0_data[14] ae19 b sdram0 bus - data bit 14 sd0_data[15] af18 b sdram0 bus - data bit 15 (lsb) sd0_dqmh ae24 o sdram0 bus - data bus mask high. active high sd0_dqml ad18 o sdram0 bus - data bus mask low. active high nsd0_ras ad25 o sdram0 bus - row address strobe. active low. also known as sdram0 command bit 2 (msb). nsd0_cas af24 o sdram0 bus - column address strobe. active low. also known as sdram0 command bit 1. nsd0_we ae23 o sdram0 bus - write enable. active low. also known as sdram0 command bit 0 (lsb). sd0_clk ae26 o sdram0 bus - clock output 1 nsd0_cs0 ad26 o sdram0 bus - chip select 0. active low pin name pin no. pin type description notes
zl10310/zl10311 data sheet 18 zarlink semiconductor inc. the provision of options, and the avoidance of the need for external pull ups, precludes the use of 5 volt tolerant inputs. the use of a 5-volt smart card would thus require external level translators. pin name pin no. function pin type description notes mod[0] t02 cio_mod[0] (msb) o common interface output - data bit 0 [msb] 1 reset_4 o bit 4 output from reset register. also mapped to pcmcia interface address bit 25. 2 mod[1] r01 cio_mod[1] o common interface output - data bit 1 1 reset_3 o bit 3 output from reset register. (pcmcia address 24) 2 mod[2] p03 cio_mod[2] o common interface output - data bit 2 1 bi_addr_8 o auxiliary external bus - address bit 8 (pcmcia address 23) 2 rt_clk o risc trace port clock output 3 mod[3] p02 cio_mod[3] o common interface output - data bit 3 1 bi_addr_9 o auxiliary external bus - address bit 9 (pcmcia address 22) 2 rt_ts6 / rt_data[7] o risc trace port 6 (debug) / risc trace data bit 7 (debug) 3 mod[4] p01 cio_mod[4] o common interface output - data bit 4 1 bi_addr_10 o auxiliary external bus - address bit 10 (pcmcia address 21) 2 rt_ts5 / rt_data[6] o risc trace port 5 (debug) / risc trace data bit 6 (debug) 3 mod[5] n02 cio_mod[5] o common interface output - data bit 5 1 bi_addr_11 o auxiliary external bus - address bit 11 (pcmcia address 20) 2 rt_ts4 / rt_data[5] o risc trace port 4 (debug) / risc trace data bit 5 (debug) 3 mod[6] m01 cio_mod[6] o common interface output - data bit 6 1 sgpio1_4 io simplified general purpose input / output bus 1 - bit 4 4 sc1_vcc_cmnd o smart card 1 interface - vcc enable output 5 bi_addr_12 o auxiliary external bus - address bit 12 (pcmcia address 19) 2 rt_ts3 / rt_data[4] o risc trace port 3 (debug) / risc trace data bit 4 (debug) 3
data sheet zl10310/zl10311 19 zarlink semiconductor inc. mod[7] m02 cio_mod[7] o common interface output - data bit 7 (lsb) 1 sgpio1_0 io simplified general purpose input / output bus 1 - bit 0 4 sc1_io b smart card 1 interface - data i/o 5 bi_addr_13 o auxiliary external bus - address bit 13 (pcmcia address 18) 2 rt_ts20 / rt_data[3] o risc trace port 20 (debug) / risc trace data bit 3 (debug) 3 moval t01 cio_mval o common interface output - data valid indicator. data valid for the current clock cycle for transmission. 1 sgpio1_2 io simplified general purpose input / output bus 1 - bit 2 4 sc1_detect i smart card 1 interface - detect input 5 bi_addr_15 o auxiliary external bus - address bit 15 (pcmcia address 16) 2 rt_ts10 / rt_data[2] o risc trace port 10 (debug) / risc trace data bit 2 (debug) 3 mostrt r03 cio_mstrt o common interface output - packet start indicator. identifies the first byte in a transport packet of 188 bytes. 1 sgpio1_3 io simplified general purpose input / output bus 1 - bit 3 4 sc1_reset o smart card 1 interface - reset output 5 bi_addr_14 o auxiliary external bus - address bit 14 (pcmcia address 17) 2 rt_ts2e / rt_data[1] o risc trace port 2e (debug) / risc trace data bit 1 (debug) 3 moclk n03 cio_mclk o common interface output - bitstream clock. 1 sgpio1_1 io simplified general purpose input / output bus 1 - bit 1 4 sc1_clk o smart card 1 interface - clock output 5 bi_addr_16 o auxiliary external bus - address bit 16 (pcmcia address 15) 2 rt_ts1e / rt_data[0] o risc trace port 1e (debug) / risc trace data bit 0 (debug) 3 pin name pin no. function pin type description notes
zl10310/zl10311 data sheet 20 zarlink semiconductor inc. note 1: multiplex setup with portmux register bits [11:10] = ?00? note 2: multiplex setup with portmux register bits [11:10] = ?10? note 3: multiplex setup with portmux register bits [11:10] = ?11? note 4: multiplex setup with portmux register bits [11:10] = '01' & cicsel3 register bit 2 = '0'. also if bi_data[7] = '0' at re set. note 5: multiplex setup with portmux register bits [11:10] = '01' & cicsel3 register bit 2 = '1'. also if bi_data[7] = '1' at re set. note 6: data inputs mid [0:7] should be connected to gnd or vdd if not required. mid[0] y02 cii_mdata[0] (msb) i common interface input - bit 0 (msb) 1, 6 bi_data[0] (msb) i auxiliary external bus - data bit 0 (msb) (pcmcia data 15) 2, 6 mid[1] y01 cii_mdata[1] i common interface input - bit 1 1, 6 bi_data[1] i auxiliary external bus - data bit 1 (pcmcia data 14) 2, 6 mid[2] t04 cii_mdata[2] i common interface input - bit 2 1, 6 bi_data[2] i auxiliary external bus - data bit 2 (pcmcia data 13) 2, 6 mid[3] u03 cii_mdata[3] i common interface input - bit 3 1, 6 bi_data[3] i auxiliary external bus - data bit 3 (pcmcia data 12) 2, 6 mid[4] v01 cii_mdata[4] i common interface input - bit 4 1, 6 bi_data[4] i auxiliary external bus - data bit 4 (pcmcia data 11) 2, 6 mid[5] v02 cii_mdata[5] i common interface input - bit 5 1, 6 bi_data[5] i auxiliary external bus - data bit 5 (pcmcia data 10) 2, 6 mid[6] u01 cii_mdata[6] i common interface input - bit 6 1, 6 bi_data[6] i auxiliary external bus - data bit 6 (pcmcia data 9) 2, 6 mid[7] t03 cii_mdata[7] (lsb) i common interface input - bit 7 (lsb) 1, 6 bi_data[7] (lsb) i auxiliary external bus - data bit 7 (lsb) (pcmcia data 8) 2, 6 mistrt u02 cii_mstrt i common interface input - packet start indicator. identifies the first byte in a transport packet of 188 bytes. miclk w02 cii_mclk i common interface input - bitstream clock. mival aa01 cii_mval i common interface input - data valid indicator. data valid for the current clock cycle for transmission. pin name pin no. function pin type description notes
data sheet zl10310/zl10311 21 zarlink semiconductor inc. 6.6 auxiliary external bus the zl1031 and zl10311 devices have an auxiliary external bus, which can be configured as an ide interface to external hard-disk drives and other atapi devices. the auxiliary bus can also offer a standard interface to external memory chips, such as flash rom etc. there are multiplexed functions on these pins, and included is information on how to access these multiplexed signals. the multiplexed functions include access to the dvb common interface address bus. the data and address pins for the auxiliary external bus are configured as ?big endian?. this means that data bit [0] and address bit [9] are the most significant bits (msb). pin name pin no. function pin type description notes bi_addr[09] a05 bi_addr[09] (msb) o auxiliary external bus - address bit 9 (msb) 1 nbi_cs5 o auxiliary external bus - chip select 5. active low. 2 bi_addr[10] a13 bi_addr[10] o auxiliary external bus - address bit 10 bi_addr[11] a15 bi_addr[11] o auxiliary external bus - address bit 11 bi_addr[12] c14 bi_addr[12] o auxiliary external bus - address bit 12 bi_addr[13] d14 bi_addr[13] o auxiliary external bus - address bit 13 bi_addr[14] b16 bi_addr[14] o auxiliary external bus - address bit 14 3 nide_iowr o ide io write signal. active low. 4 ndvb_ci_iowr o dvb common interface io write signal 5 bi_addr[15] a17 bi_addr[15] o auxiliary external bus - address bit 15 3 nide_iord o ide io read signal. active low. 4 ndvb_ci_iord o dvb common interface io read signal 5 bi_addr[16] b17 bi_addr[16] o auxiliary external bus - address bit 16 bi_addr[17] a18 bi_addr[17] o auxiliary external bus - address bit 17 6 dvb_ci_a[14] (msb) o dvb common interface address bit 14 (msb) 5 bi_addr[18] c16 bi_addr[18] o auxiliary external bus - address bit 18 6 dvb_ci_a[13] o dvb common interface address bit 13 5 bi_addr[19] b18 bi_addr[19] o auxiliary external bus - address bit 19 6 dvb_ci_a[12] o dvb common interface address bit 12 5 bi_addr[20] d16 bi_addr[20] o auxiliary external bus - address bit 20 6 dvb_ci_a[11] o dvb common interface - address bit 11 5 bi_addr[21] c17 bi_addr[21] o auxiliary external bus - address bit 21 6 dvb_ci_a[10] o dvb common interface - address bit 10 5
zl10310/zl10311 data sheet 22 zarlink semiconductor inc. bi_addr[22] b19 bi_addr[22] o auxiliary external bus - address bit 22 6 dvb_ci_a[9] o dvb common interface - address bit 9 5 bi_addr[23] a21 bi_addr[23] o auxiliary external bus - address bit 23 6 dvb_ci_a[8] o dvb common interface - address bit 8 5 bi_addr[24] c19 bi_addr[24] o auxiliary external bus - address bit 24 6 dvb_ci_a[7] o dvb common interface - address bit 7 5 bi_addr[25] c20 bi_addr[25] o auxiliary external bus - address bit 25 6 dvb_ci_a[6] o dvb common interface - address bit 6 5 bi_addr[26] b21 bi_addr[26] o auxiliary external bus - address bit 26 6 dvb_ci_a[5] o dvb common interface - address bit 5 5 bi_addr[27] c21 bi_addr[27] o auxiliary external bus - address bit 27 6 dvb_ci_a[4] o dvb common interface - address bit 4 5 bi_addr[28] b22 bi_addr[28] o auxiliary external bus - address bit 28 6 dvb_ci_a[3] o dvb common interface - address bit 3 5 bi_addr[29] a23 bi_addr[29] o auxiliary external bus - address bit 29 6 dvb_ci_a[2] o dvb common interface - address bit 2 5 bi_addr[30] c22 bi_addr[30] o auxiliary external bus - address bit 30 6 dvb_ci_a[1] o dvb common interface - address bit 1 5 bi_addr[31] a24 bi_addr[31] (lsb) / bi_wbe1 o auxiliary external bus - address bit 31 (lsb) / write byte enable bit 1 6 dvb_ci_a[0] (lsb) o dvb common interface address bit 0 (lsb) 5 bi_data[00] g02 bi_data[00] (msb) o auxiliary external bus - data bit 0 (msb) bi_data[01] f01 bi_data[01] o auxiliary external bus - data bit 1 bi_data[02] h03 bi_data[02] o auxiliary external bus - data bit 2 bi_data[03] g03 bi_data[03] o auxiliary external bus - data bit 3 bi_data[04] f02 bi_data[04] o auxiliary external bus - data bit 4 bi_data[05] e01 bi_data[05] o auxiliary external bus - data bit 5 bi_data[06] f03 bi_data[06] o auxiliary external bus - data bit 6 bi_data[07] e02 bi_data[07] o auxiliary external bus - data bit 7 bi_data[08] d01 bi_data[08] o auxiliary external bus - data bit 8 pin name pin no. function pin type description notes
data sheet zl10310/zl10311 23 zarlink semiconductor inc. bi_data[09] f04 bi_data[09] o auxiliary external bus - data bit 9 bi_data[10] e03 bi_data[10] o auxiliary external bus - data bit 10 bi_data[11] d02 bi_data[11] o auxiliary external bus - data bit 11 bi_data[12] c01 bi_data[12] o auxiliary external bus - data bit 12 bi_data[13] b01 bi_data[13] o auxiliary external bus - data bit 13 bi_data[14] c02 bi_data[14] o auxiliary external bus - data bit 14 bi_data[15] d03 bi_data[15] (lsb) o auxiliary external bus - data bit 15 (lsb) nbi_cs0 b13 nbi_cs0 o auxiliary external bus - chip select 0. active low. disabled if internal boot rom enabled. used for flash rom. nbi_cs1 c13 nbi_cs1 o auxiliary external bus - chip select 1. active low. 6 ndvb_ci_card _enable o dvb common interface - card enable. active low. 5 nbi_cs2 a12 nbi_cs2 o auxiliary external bus - chip select 2. active low. 8 nide_cs0 ide bus chip select 0. active low. 9 nbi_cs3 b11 nbi_cs3 o auxiliary external bus - chip select 3. active low. 8 nide_cs1 o ide bus chip select 1. active low. 9 nbi_oe c11 nbi_oe o auxiliary external bus - output enable for all aux. bus devices (including common interface). active low. 6 dvb_ci_oe o dvb common interface - output enable. active low. 5 bi_ready c04 bi_ready i 5v auxiliary external bus - data ready input. optional transfer complete signal from an external device. 6 dvb_ci_wait o 5v dvb common interface - wait. 5 bi_rnw b07 bi_rnw o auxiliary external bus - read/not write output. nbi_wbe0 b12 nbi_wbe0 o auxiliary external bus - write byte enable 0. active low. 6 dvb_ci_we o dvb common interface - write-enable output. 5 pin name pin no. function pin type description notes
zl10310/zl10311 data sheet 24 zarlink semiconductor inc. note 1: multiplex setup with portmux register bit [7] = ?0? note 2: multiplex setup with portmux register bit [7] = ?1? note 3: multiplex setup with cic control register bit 3 = '1', & bit 30 or bit 31 = '0' note 4: multiplex setup with cic control register bit 3 = '1', & bit 30 or bit 31 = '1' note 5: multiplex setup with cic control register bit 3 = '0' note 6: multiplex setup with cic control register bit 3 = '1' 6.7 peripheral port the peripheral port is provided with 10 pins that can be configured as general purpose i/o bits, or can provide several alternative interfaces. the bit i/os are provided by the gpis (input) and gpos (output) registers, along with the portmux and cic control register bits, and only the bits listed below should be used. there are multiplexed functions on these pins, and included is information on how to access these multiplexed signals. the multiplexed functions include access to gpio signals, dma control signals, infrared port, serial communications port, s/pdif audio bitstream output and some ancillary common interface video control signals. nedmac3_ack b06 nedmac3_ack o external dma port 3 acknowledge output for an ide controller. active low. nide_dma_ack o ide acknowledge output. active low. nedmac3_req a06 nedmac3_req i external dma port 3 request input from an ide controller. active low. nide_dma_req i ide dma request input. active high. nide_oe ad16 nide_oe o ide output enable signal for a bus transceiver in the ide data path. active low. int2 e24 int2 i powerpc ? external interrupt #2 input. connect to vdd_io or ground if not required. pin name pin no. function pin type description multiplex configuration pp[0] c12 gpio_22 io general purpose input/output - bit 22 portmux reg. bit 8 = '0', gpos reg bits 44:45 = '00' int9 i powerpc ? external interrupt #9 input portmux reg bit 8 = '0', gpis3 reg bits 44:45 = '01' edmac2_ack o dma channel 2 external acknowledge output portmux reg bit 8 = '1', cic control reg bits 26:27 = '10' ebm_holdack io external bus master (master/slave bus arbitration controls) - hold acknowledge flag portmux reg bit 8 = '1', cic control reg bits 26:27 = '11' pin name pin no. function pin type description notes
data sheet zl10310/zl10311 25 zarlink semiconductor inc. pp[1] f23 gpio_04 io general purpose input/output - bit 4 portmux reg bit 8 = '0', gpos reg bits 8:9 = '00' nsd1_cs1 o sdram1 bus - chip select 1. active low portmux reg bit 8 = '0', gpos reg bits 8:9 = '10' nedmac2_req i dma channel 2 external request input. active low. portmux reg bit 8 = '1', cic control reg bits 26:27 = '10' ebm_holdreq io external bus master (master/slave bus arbitration controls) - hold request flag portmux reg bit 8 = '1', cic control reg bits 26:27 = '11' pp[2] ae05 gpio_24 io general purpose input/output - bit 24 portmux reg bit 3 = '0' serial1/ infrared_rxd i serial port 1 / irda port receive data portmux reg bit 3 = '1' pp[3] ac16 gpio_25 io general purpose input/output - bit 25 portmux reg bit 3 = '0' serial1/ infrared_txd o serial port 1 / irda port transmit data portmux reg bit 3 = '1' pp[4] ad17 gpio_08 io general purpose input/output - bit 8 portmux reg bit 13 = '0', gpos reg bits 16:17 = '00' scp_clk o serial communications port - baud-rate clock output portmux reg bit 13 = '0', gpos & gpis1 reg bits 16:17 = '01' sysclk o system clock output (54mhz) portmux reg bit 13 = '1' pp[5] ad09 gpio_07 io general purpose input/output - bit 7 portmux reg bit 2 = '0', gpos reg bits 14:15 = '00' scp_rxd i serial communications port - receive data input portmux reg bit 2 = '0', gpis1 reg bits 14:15 = '01' edmac2_eot io dma channel 2 external end of transfer portmux reg bit 2 = '1', cic control reg bits 26:27 = '10' ebm_busreq io external bus master - bus request flag (master/slave bus arbitration controls) portmux reg bit 2 = '1', cic control reg bits 26:27 = '11' pin name pin no. function pin type description multiplex configuration
zl10310/zl10311 data sheet 26 zarlink semiconductor inc. note 1: dv_ transparency_ gate output controlled by the osd bitmap; used to control the drivers of another pixel bus. programmable polarity. 6.8 modem/codec interface this interface allows a full 16550-compatible uart interface, a standard serial port for irda, and a synchronous rs232-compatible modem interface. there is also provision for 4 gpio ports. when mcp7:4 provide a 4-wire codec interface, mcp3:0 would normally be used to provide four more general purpose i/o bits but can alternatively supply additional serial 1 flags. when a full rs232 modem interface is required, the complete mcp interface must be used for serial 0 signals. pp[6] af02 gpio_06 io general purpose input/output - bit 6 portmux reg bit 2 = '0', gpos reg bits 12:13 = '00' scp_txd o serial communications port - transmit data output portmux reg bit 2 = '0', gpos reg bits 12:13 = '01' ci_packet_ start i dvb common interface - transport packet start indicator. portmux reg bit 2 = '0', gpis2 reg bits 12:13 = '01' int3 b powerpc ? external interrupt #3 input portmux reg bit 2 = '1' pp[7] ae10 gpio_18 io general purpose input/output - bit 18 portmux reg bit 4 = '0', gpos reg bits 36:37 = '00' dv_ transparency _ gate io reserved portmux reg bit 4 = '0', gpos & gpis1 reg bits 36:37 = '01' serial1 /infrared_clk i serial port 1 / irda port clock input portmux reg bit 4 = '0', gpis3 reg bits 36:37 = '01' serial1 /infrared _ncts i serial port 1 / irda port clear-to-send input. active low. portmux reg bit 4 = '1'. over-ruled when portmux reg bits 6:5 = '10' to select the serial1 cts input on mcp[1]. pp[8] c09 gpio_21 io general purpose input/output - bit 21 portmux reg bit 0 = '0', gpos reg bit 42:43 = '00' int8 i powerpc ? external interrupt #8 input portmux reg bit 0 = '0', gpis3 reg bit 42:43 = '01' da_iec958 o digital audio s/pdif (iec 958) serial data output portmux reg bit 0 = '1' pp[9] ac25 gpio_05 io general purpose input/output - bit 5 portmux reg bit 1 = '0', gpos reg bits 10:11 = '00' nsd0_cs1 o sdram0 bus - chip select 1. active low portmux reg bit 1 = '0', gpos reg bits 10:11 = '10' dv1_pixel_ clock o reserved portmux reg bit 1 = '1' pin name pin no. function pin type description multiplex configuration
data sheet zl10310/zl10311 27 zarlink semiconductor inc. the software options provided allow a full interface to an external modem, using the serial 0 interface, whilst still leaving a basic serial 1 interface on the peripheral port (see section 6 above, in the pin descriptions section). note 1: multiplex setup with portmux register bits [6:5] = ?11? pin name pin no. function pin type description notes mcp[0] t24 serial0/16550_ri i serial port 0 / 16550 uart ring indicator input 1 serial1/infrared_ rts o serial port 1 / irda port request-to-send output 2 gpio_28 io general purpose input/output - bit 28 3 mcp[1] v25 serial0/16550_dcd i serial port 0 / 16550 uart data carrier detect input 1 nserial1/infrared_ cts i serial port 1 / irda port clear-to-send input. active low. 2 gpio_27 io general purpose input/output - bit 27 3 mcp[2] p23 serial0/16550_dtr o serial port 0 / 16550 uart data terminal ready output 1 serial1/infrared_ dtr o serial port 1 / irda port data terminal ready output 2 gpio_26 io general purpose input/output - bit 26 3 mcp[3] u26 serial0/16550_dsr i serial port 0 / 16550 uart data set ready input 1 serial1/infrared_ dsr i serial port 1 / irda port data set ready input 2 gpio_23 io general purpose input/output - bit 23 3 mcp[4] t26 serial0/16550_txd o serial port 0 / 16550 uart transmit data output 4 ssp_txd o synchronous serial port for modem - transmit data output 5 mcp[5] u25 serial0/16550_rxd i 5v serial port 0 / 16550 uart receive data input 4 ssp_rxd i 5v synchronous serial port for modem - received data input 5 mcp[6] v26 nserial0/16550_cts i 5v serial port 0 / 16550 uart clear-to-send input. active low. 4 ssp_clk i 5v synchronous serial port for modem - baud rate clock 5 mcp[7] p24 nserial0/16550_rts o 5v serial port 0 / 16550 uart request-to-send output. 4 ssp_fs io 5v synchronous serial port for modem - frame sync 5
zl10310/zl10311 data sheet 28 zarlink semiconductor inc. note 2: multiplex setup with portmux register bits [6:5] = ?10? note 3: multiplex setup with portmux register bits [6:5] = ?0x? note 4: multiplex setup with cic control register bit 2 = ?0? and bit 28 = ?1? note 5: multiplex setup with cic control register bits 2 = ?1?, bit 28 = '1' and cicsel3 register bit 6 = '0' 6.9 smart card interface note 1: multiplex setup with cicsel3 register bit 1 = '0'. also if bi_data[6] = '0' at reset. note 2: multiplex setup with cicsel3 register bit 1 = '1'. also if bi_data[6] = '1' at reset. 6.10 general purpose input output interfaces the general purpose input output interface is provided with 10 pins that can be configured as general purpose i/o bits, or can provide several alternative interfaces. the bit i/os are provided by the gpis (input) and gpos (output) registers, and only the bits listed below should be used. care should be observed when programming the registers allocated to each of the gpio ports. there are multiplexed functions on these pins, and included is information on how to access these multiplexed signals. the multiplexed functions include access to gpio signals, i 2 c bus, i 2 s audio output signals, test interface signals, clock signals, video sync signals, synchronous serial port signals and a vcxo error signal. pin name pin no. function pin type description notes sgpio0[0] ad05 sgpio0_0 io 5v simplified general purpose input / output bus 0 - bit 0 1 sc0_io b 5v smart card 0 interface - data i/o 2 sgpio0[1] ac03 sgpio0_1 io 5v simplified general purpose input / output bus 0 - bit 1 1 sc0_clk o 5v smart card 0 interface - clock output 2 sgpio0[2] af04 sgpio0_2 io 5v simplified general purpose input / output bus 0 - bit 2 1 sc0_detect i 5v smart card 0 interface - detect input 2 sgpio0[3] ad06 sgpio0_3 io 5v simplified general purpose input / output bus 0 - bit 3 1 sc0_reset o 5v smart card 0 interface - reset output 2 sgpio0[4] af03 sgpio0_4 io 5v simplified general purpose input / output bus 0 - bit 4 1 sc0_vcc_command o 5v smart card 0 interface - vcc enable output 2
data sheet zl10310/zl10311 29 zarlink semiconductor inc. pin name pin no. function pin type description multiplex configuration gp00 af16 gpio_00 io general purpose input/output - bit 0 gpos reg bits 0:1 = '00' i2c1_scl b i 2 c (inter integrated circuit) bus 1 serial clock io gpos reg bits 0:1 =?01? gpis1 reg bits 0:1 = '01' da_deemphasis0 o digital audio de-emphasis indicator bit 0 output. (see note 1). gpos reg bits 0:1 = '10' da_surmod0 o digital audio dolby surround mode bit 0. (see note 2) gpos reg bits 0:1 = '11' test_mode_a i device test mode a enable. (see note 4) - gp01 ad04 gpio_01 io general purpose input/output - bit 1 gpos reg bits 2:3 = '00' i2c1_sda b i 2 c (inter integrated circuit) bus 1 serial data io gpos reg bits 2:3 =?01? gpis1 reg bits 2:3 = '01' da_deemphasis1 o digital audio de-emphasis indicator bit 1 output. (see note 1). gpos reg bits 2:3 = '10' da_surmod1 o digital audio dolby surround mode bit 1. (see note 2) gpos reg bits 2:3 = '11' debug_mode i debug-mode enable. (see note 4) - gp02 ac06 gpio_02 io 5v general purpose input/output - bit 2 gpos reg bits 4:5 = '00' av_csync i 5v digital composite video sync output gpis1 reg bits 4:5 = '01' nbi_cs4 o 5v auxiliary external bus - chip select 4. active low. gpos reg bits 4:5 = '01' da_surmod0 o 5v digital audio dolby surround mode bit 0. (see note 2) gpos reg bits 4:5 = '11' int4 i 5v powerpc ? external interrupt #4 input gpis reg bits 4:5 = ?11?
zl10310/zl10311 data sheet 30 zarlink semiconductor inc. gp03 af12 gpio_03 io general purpose input/output - bit 2 gpos reg bits 6:7 = '00' sys_clk o system clock output (54mhz) gpos reg bits 6:7 = '01' nbi_cs5 o auxiliary external bus - chip select 5. active low. gpos reg bits 6:7 = '10' int5 i powerpc ? external interrupt #5 input gpis3 reg bits 6:7 = '01' da_surmod1 o digital audio dolby surround mode bit 1. (see note 2) gpos reg bits 6:7 = '11' pm15 i boot-option input - map to portmux register bit 15. (see note 5). - gp10 ad07 gpio_10 io general purpose input/output - bit 10 gpos reg bits 20:21 = '00' gpt_capt1 i general purpose timer - capture timer 1 input. typically an interrupt from an infrared receiver. gpis3 reg bits 20:21 = '01' nbi_cs7 o auxiliary external bus - chip select 7. active low. gpos reg bits 20:21 = '11' gp16 a04 gpio_16 io general purpose input/output - bit 16 gpos reg bits 32:33 = '00' da_serial_data1 o digital audio serial data. surround channel serial audio data at a rate of 64fs. (dolby-enabled devices only) gpos reg bits 32:33 = '01' nbi_cs4 o auxiliary external bus - chip select 4. active low. gpos reg bits 32:33 = '10' gp17 c07 gpio_17 io general purpose input/output - bit 17 gpos reg bits 34:35 = '00' da_serial_data2 o digital audio serial data. centre channel/subwoofer serial audio data at a rate of 64fs. (dolby-enabled devices only) gpos reg bits 34:35 = '01' nbi_cs5 o auxiliary external bus - chip select 5. active low. gpos reg bits 34:35 = '10' pm14 i boot-option input - map to portmux register bit 14. (see note 5). - pin name pin no. function pin type description multiplex configuration
data sheet zl10310/zl10311 31 zarlink semiconductor inc. note 1: da_deemphasis [1:0] have following truth-table: ?00? = no emphasis, ?01? = 50-15 ms emphasis, ?10? = reserved, ?11? = ccitt j.17 note 2: da_surmod[1:0] used to indicate whether dolby digital encoded stream has been encoded in dolby surround. note 3: da_lr_ch_clk (via gp19) is a clock whose phase indicates the presence of left hand or right hand data, and whose rate is equivalent to fs. signal routed through to gp14 (not bonded out). note 4: gp00 and gp01 inputs are latched during power-up only. active low input at power-up to enable boot mode functions. note 5: gp03 and gp17 inputs are latched at power-up only. note 6: gp29 xpt_pwm_output compensates for frequency errors in 27mhz external vcxo. 6.11 simplified general purpose input output interface the simplified general purpose input output interface is provided with 8 pins that can be configured as general purpose i/o bits. as there is only one mapped sgpio signal mapped to each of the pins, the interface is simple, with sgpio inputs monitored using the sgpi input register, and outputs set using the sgpo register. the reserved signals are configured as ?big endian?. this means that dv1_data [0] is the most significant bit (msb). gp19 d21 gpio_19 io 5v general purpose input/output - bit 19 gpos reg bits 38:39 = '00' gpt_capt0 i 5v general purpose timer - capture timer 0 input gpis1 reg bits 38:39 = '01' dv2_vsync io 5v reserved gpos reg bits 38:39 = '10', gpis2 reg bits 38:39 = '01' ssp_fs i 5v synchronous serial port for modem - frame sync gpis2 reg bits 28:29 = '01' da_lr_ch_clk i 5v i 2 s digital audio left-right channel indicator input. (see note 3) cicsel3 reg bit 6 = '1', gpis2 reg bits 28:29 = '01' gp20 ac11 gpio_20 io 5v general purpose input/output - bit 20 gpos reg bits 40:41 = '00' int23 i 5v powerpc ? external interrupt #5 input gpis1 reg bits 40:41 = '01' dv2_hsync io 5v reserved gpos reg bits 40:41 = '10', gpis2 reg bits 40:41 = '01' ssp_clk i 5v synchronous serial port for modem - baud rate clock gpis3 reg bits 40:41 = '01' da_bit_clk i 5v i 2 s digital audio 64fs clock input. signal routed through to gp13 (not bonded out) cicsel3 reg bit 6 = '1', gpis2 reg bits 26:27 = '01' gp29 ae04 gpio_29 io 5v general purpose input/output - bit 29 gpos reg bits 58:59 = '00' xpt_pwm_output o 5v system vcxo pulse-width modulated error signal. (see note 6) gpos reg bits 58:59 = '10' pin name pin no. function pin type description multiplex configuration
zl10310/zl10311 data sheet 32 zarlink semiconductor inc. note 1: multiplex setup with cicsel3 register bit 3 = '0' note 2: multiplex setup with cicsel3 register bit 3 = '1' note 3: latched input. must not be pulled low during chip reset. note 4: cicvcr register bit 23 = ?1? sets dv1_data to an output, ?0? sets to an input pin name pin no. function pin type description notes sgpio2[0] a11 sgpio2_0 io simplified general purpose input / output bus 2 - bit 0 1 dv1_data[0] (msb) b reserved 2, 3 sgpio2[1] b10 sgpio2_1 io simplified general purpose input / output bus 2 - bit 1 1 dv1_data[1] b reserved 2, 3 sgpio2[2] b08 sgpio2_2 io simplified general purpose input / output bus 2 - bit 2 1 dv1_data[2] b reserved 2, 3 sgpio2[3] b09 sgpio2_3 io simplified general purpose input / output bus 2 - bit 3 1 dv1_data[3] b reserved 2, 3 boot_mode i boot mode. latched during power-up only. pull low with resistor to boot from internal rom. leave floating to boot via external memory via bi_cs0. sgpio2[4] c10 sgpio2_4 io simplified general purpose input / output bus 2 - bit 4 1 dv1_data[4] b reserved 2, 3, 4 sgpio2[5] a09 sgpio2_5 io simplified general purpose input / output bus 2 - bit 5 1 dv1_data[5] b reserved 2, 3, 4 sgpio2[6] a07 sgpio2_6 io simplified general purpose input / output bus 2 - bit 6 1 dv1_data[6] b reserved 2, 3, 4 sgpio2[7] c08 sgpio2_7 io simplified general purpose input / output bus 2 - bit 7 1 dv1_data[7] (lsb) b reserved 2, 3, 4
data sheet zl10310/zl10311 33 zarlink semiconductor inc. 6.12 inter integrated circuit (i 2 c) interface the i 2 c interface provides a highly programmable interface to the industry-standard i 2 c (inter-integrated circuit) serial bus. the i 2 c device contains a selection of functions that can be programmed to operate as a master, as a slave, or as both a master and a slave on the i 2 c interface. i 2 c, unlike other designs, requires a minimum amount of software to manage the i 2 c bus. in addition to sophisticated i 2 c bus protocol management, the i 2 c device provides full data buffering, eliminating any time-dependent program interaction and further simplifying the task of connecting to the i 2 c bus. the i 2 c interface complies with the philips ? semiconductors i 2 c specification, dated 1995. both the scl and sda pins require an external pull-up to 3.3v; minimum resistor value of 1067 ohms. 6.13 inter ic sound (i 2 s) audio interface the pcm audio output controller provides an i 2 s audio interface. the audio outputs can be internally muted, and a separate control output is not required. s/pdif, surround, and center serial outputs can be obtained by using peripheral or general purpose port pins. 6.14 clock and reset interface the clock and reset interface provides inputs for the 2 primary clock signals, and also a system reset input. pin name pin no. pin type description i2c0_scl r25 o i 2 c bus clock. dedicated open drain clock. i2c0_sda r26 o i 2 c bus data. dedicated open drain serial data/address. pin name pin no. pin type description da_bit_clk c06 o digital audio 64fs clock output da_lr_ch_clk b04 o digital audio left-right channel indicator output. a clock whose phase indicates the presence of left hand or right hand data, and whose rate is equivalent to fs. da_osamp_clk a03 o digital audio oversampling clock output. 512/256 fs clock da_ser_data0 d06 o digital audio serial data output. main left and right serial audio data at a rate of 64fs pin name pin no. pin type description osc_pad c05 cofdm crystal oscillator - 20.48mhz crystal connection positive. also external 20.48mhz cxo input osc_padn b03 cofdm crystal oscillator - 20.48mhz crystal connection negative. clk27_in c18 i main system clock input - 27mhz from external vcxo ng_sys_rst a20 i power-on reset input, from external por generator. active low. must be held low for at least 100 microseconds after the 1.8v supply has been established. tmode b05 i connect to gnd in normal operation. defines production test mode b
zl10310/zl10311 data sheet 34 zarlink semiconductor inc. 6.15 power supply pins the zl10310 and zl10311 devices operate from 3 voltages; 3.3v for the input/outputs, 2.5v for the video dacs and 1.8v for the soc core. the table below shows the pins to which each of the supply voltages should be connected. pin name pin no.s description nominal voltage supply gnd a1, a2, a8, a14, a19, a26, b2, b25, b26, c3, c24, d4, d9, d13, d18, d23, h1, h26, j4, j23, n1, n23, p4, p26, v4, v23, w1, w26, ac4, ac9, ac14, ac18, ac23, ad3, ad24, ae1, ae2, ae25, af1, af8, af13, af19, af25, af26 digital ground (used in parallel with thermal_gnd pins) 0v vdd_core d10, d12, d15, d17, k4, k23, m4, m23, r4, r23, u4, u23, ac10, ac12, ac15, ac17 vdd supplies to zl10310/zl10311 core +1.8v wrt gnd vdd_io ac5, ac7, ac8, ac19, ac20, ac22, e23, g23, h23, w23, y23, ab23, d5, d7, d8, d19, d20, d22, e4, g4, h4, w4, y4, ab4 vdd supplies to zl10310/zl10311 i/o pins +3.3v wrt gnd aud_gnda0 b14 analog gnd for audio pll 1 0v aud_gnda1 c15 analog gnd for audio pll 2 0v aud_vdda0 b15 analog vdd for audio pll 1 +1.8v wrt aud_gnd aud_vdda1 a16 analog vdd for audio pll 2 +1.8v wrt aud_gnd clk_gnda a22 analog gnd for system clock pll (27mhz) 0v clk_vdda b20 analog vdd for system clock pll (27mhz) +3.3v wrt clk_gnd cofdm_gnda a10 analog gnd for cofdm pll (20.48mhz) 0v cofdm_vdda d11 analog vdd for cofdm pll (20.48mhz) +1.8v wrt cofdm_gnd dac1_agnd ae12, ad14, ae16 analog gnd for video triple-dac 1 0v dac1_avdd ac13, af14, af15, ae17 analog vdd for video triple-dac 1 +2.5v wrt dac1_agnd dac2_agnd af09, ae08, ae07 analog gnd for video triple-dac 2 0v
data sheet zl10310/zl10311 35 zarlink semiconductor inc. 6.16 reserved connections the following pins have no specific function allocated, and are reserved. dac2_avdd ad12, ad11, ae06, ad08 analog vdd for video triple-dac 2 +2.5v wrt dac2_agnd thermal_gnd l11, l12, l13, l14, l15, l16, m11, m12, m13, m14, m15, m16, n11, n12, n13, n14, n15, n16, p11, p12, p13, p14, p15, p16, r11, r12, r13, r14, r15, r16, t11, t12, t13, t14, t15, t16 thermal ground pins (used in parallel with digital gnd pins (gnd)) 0v pin no. pin type connection w25 analog io not connected u24 analog io not connected r24 analog io not connected t25 analog io not connected ae03 o 5v not connected ad01 o 5v not connected ad02 o 5v not connected ab03 b 5v not connected pin name pin no.s description nominal voltage supply
zl10310/zl10311 data sheet 36 zarlink semiconductor inc. 7.0 characteristics 7.1 ac and dc electrical characteristics absolute maximum ratings parameter min max units supply voltage wrt gnd, 1.8 v supply +2.3 v supply voltage wrt gnd, 2.5v supply +3.0 v supply voltage wrt gnd, 3.3 v supply +3.9 v storage temperature -65 150 c bias for 5v inputs +5.5 v input voltage (any input pin) (gnd?0.5) (vdd_io+0.5) v output voltage (any output pin) (gnd?0.5) (vdd_io+0.5) v esd rating (static discharge) 3k v max junction temperature 110 c dc characteristics symbol parameter min typ max unit conditions ta operating free air temperature 0 70 c jc thermal resistance, junction to case 18 c/watt vdd_core digital core supply voltage 1.71 1.80 1.89 v vdd_io digital io supply voltage 3.14 3.30 3.47 v aud_vdda0, 1 audio clock pll supply voltage 1.71 1.80 1.89 v clk_vdda system clock pll supply voltage 3.14 3.30 3.47 v cofdm_vdda cofdm oscillator supply voltage 1.71 1.80 1.89 v dac1_avdd video triple-dac 1 supply voltage 2.38 2.50 2.62 v dac2_avdd video triple-dac 2 supply voltage 2.38 2.50 2.62 v idd_core supply current, 1.8 v 550 750 ma vdd_core = max idd_dacs supply current, 2.5 v 80 100 ma dacx_avdd = max
data sheet zl10310/zl10311 37 zarlink semiconductor inc. idd_io supply current, 3.3 v 40 75 ma vdd_io = max pd power dissipation 1.78 2.0 w all vdd pins = max clk27_in_freq system input clock frequency 27 mhz external vcxo cofdm_osc_ freq cofdm input clock frequency 20.48 mhz external crystal oscillator cofdm_osc_tol cofdm crystal oscillator to le ra n c e 50 ppm dc characteristics symbol parameter min typ max unit conditions
zl10310/zl10311 data sheet 38 zarlink semiconductor inc.
c zarlink semiconductor 2002 all rights reserved. apprd. issue date acn package code previous package codes i 1 2 1 - - - - - - - - - - - - 1 213807 25nov02
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